OPB - On-chip Peripherial Bus AXI – Advance eXtensible Interface by Ernest Jamro Katedra Elektroniki, AGH Kraków

Przykład magistrali OPB OPB – magistrala wewnętrzna, łącząca moduły wewnątrz pojedynczego układu scalonego

OPB, AXI Magistrale synchroniczne Wszystkie sygnały są próbkowane wraz z narastającym sygnałem zegarowym.

Różne rodzaje urządzeń: Master – inicjuje transfer: podaje sygnał gotowości do transmisji (sygnał Select lub adres na magistrale adresową, dane (w przypadku zapisu) na magistralę Slave (OPB) – zachowuje się podobnie jak pamięć – czyli odczytuje adres i wystawia dane (w przypadku odczytu). Arbiter – Transmisja jest wykonywana tylko pomiędzy jednym urządzeniem Master i jednym urządzeniem Slave. Dlatego Arbiter przyznaje magistrale wybranemu pojedynczemu urządzeniu Master (Initiator) w wybranej chwili czasowej.

Współdzielenie (multipleksacja) sygnałów na magistrali OPB

Fizyczne połączenie sygnałów magistrali OPB

Prosty sposób transakcji - OPB Urządzenie Master gotowe do transmisji: Select=‘1’ Urządzenie Slave odpowiada, że jest gotowe do transmisji: Ack=‘1’ Transfer danych tylko wtedy kiedy Ack=‘1’ (przy narastającym sygnale zegarowym – magistrala synchroniczna)

Prosty sposób transakcji - AXI Valid przed Ready Ready przed Valid

Algorytm Arbitrażu 1 Stały priorytet – każde urządzenie ma określony priorytet i magistrala jest przydzielana według priorytetu (urządzenie żądające magistrali o najwyższym priorytecie dostaje magistrale. OPB_M0Grant<= M0_request -- [M0 – najwyższy priorytet] OPB_M1Grant<= M1_request and not M0_request OPB_M2Grant<= M2_request and not (M0_request or M1_request) OPB_M3Grant<= M3_request and not (M0_request or M1_request or M2_request)

Algorytm Arbitrażu 2 Dynamiczny Priorytet – np. Least Recently Used (LRU) algorytm, dla którego po każdym arbitrażu magistrali Master, który ostatnio otrzymał magistralę ma ustawiony priorytet na najniższy, pozostałym urządzeniom priorytet jest podnoszony o 1. M0_Priorytet<= 0 -- [M0 – przyznano właśnie magistra] M1_Priorytet<= M1_Priorytet + 1 M2_Priorytet<= M2_Priorytet + 1 ...

Arbitraż Magistrali OPB

Pojedynczy odczyt na OPB

Pojedynczy odczyt i zapis na OPB

Adresowanie sekwencyjne

Podstawowa funkcja modułu slave Dekodowanie czy adres na magistrali Adres jest w zakresie lokacji adresowej urządzenia Slave (czyli od C_BASEADDR do C_HIGHADDR) Wystawienie sygnału ACK tylko wtedy, kiedy jest adresowane urządzenie użytkownika Kopiowanie stanu sygnałów drd na magistralę Sl_DBus w przypadku odczytu OPB_RNW=1 i aktywnego urządzenia

Budowa własnego modułu Slave (tylko zapis do rejestru)

AXI lite IPIF

IPIF User Ports 1 Bus2IP_Addr Bus2IP_Addr is a 32-bit vector that drives valid when Bus2IP_CS and Bus2IP_RdCE or Bus2IP_WrCE drives high. Bus2IP_Data Bus2IP_Data is a vector of width C_S_AXI_DATA_WIDTH and drives valid on writes when Bus2IP_WrCE is high. Bus2IP_RNW Bus2IP_RNW is a signal indicating the type of transfer in progress and is valid when Bus2IP_CS and Bus2IP_WrCE or Bus2IP_RdCE is asserted. A high on Bus2IP_RNW indicates the transfer request is a read of the user IP. A low on Bus2IP_RNW indicates the transfer request is a write to the user IP. Bus2IP_CS Bus2IP_CS is a vector of width C_ARD_ADDR_RANGE_ARRAY length / 2. In other words, for each address pair defined in C_ARD_ADDR_RANGE_ARRAY there is one Bus2IP_CS defined. This signal asserts at the beginning of a valid cycle on the IPIC. This signal used in conjunction with Bus2IP_RNW is especially suited for reading and writing to memory type devices. Bus2IP_RdCE Bus2IP_RdCE is a vector of a width that is the sum total of the values defined in C_ARD_NUM_CE_ARRAY. For each address pair defined in C_ARD_ADDR_RANGE_ARRAY, a number of CEs can be defined in C_ARD_NUM_CE_ARRAY. Bus2IP_RdCE goes High coincident with Bus2IP_CS for read type transfers and is especially suited for reading registers.

IPIF User Ports 2 Bus2IP_WrCE Bus2IP_WrCE is a vector of a width that is the sum total of the values defined in C_ARD_NUM_CE_ARRAY. For each address pair defined in C_ARD_ADDR_RANGE_ARRAY, a number of CEs can be defined in C_ARD_NUM_CE_ARRAY. Bus2IP_WrCE goes High when the write data is valid on Bus2IP_WrCE and is especially suited for writing to registers. IP2Bus_Data IP2Bus_Data is a vector of width C_S_AXI_DATA_WIDTH and is the read data bus. Read data should be valid when IP2Bus_RdAck is asserted by the user IP. IP2Bus_RdAck IP2Bus_RdAck is the read data acknowledge signal. This signal is used by the user IP to acknowledge a read cycle and causes read control signals, Bus2IP_RdCE, Bus2IP_CS and Bus2IP_RNW to deassert. IP2Bus_WrAck IP2Bus_WrAck is the write data acknowledge signal. This signal is used by the user IP to acknowledge a write cycle and causes write control signals, Bus2IP_WrCE, and Bus2IP_CS to deassert.

IPIF Usage example GPIO - General Purpose Input Output process (Bus2IP_Clk) begin if Bus2IP_Clk 'event and Bus2IP_Clk ='1' then if Bus2IP_WrCE(0)= '1' then GPIO_OUT <= Bus2IP_Data; end if; end process; IP2Bus_WrAck <= Bus2IP_WrCE(0); -- Input IP2Bus_Data <= GPIO_In; IP2Bus_RdAck <= Bus2IP_RdCE(0);

IPIF GPIO2 –2 Ports -- OUTPUT process (Bus2IP_Clk) begin if Bus2IP_Clk 'event and Bus2IP_Clk ='1' then if Bus2IP_WrCE(0)= '1' then GPIO_OUT0 <= Bus2IP_Data; end if; if Bus2IP_WrCE(1)= '1' then GPIO_OUT1 <= Bus2IP_Data; end process; IP2Bus_WrAck <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1); -- Input IP2Bus_Data <= GPIO_In0 when Bus2IP_RdCE(0) else GPIO_In1; IP2Bus_RdAck <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1);

IPIF – BRAM memory BRAM_Adr<= Bus2IP_Addr; BRAM_Din<= Bus2IP_Data; IP2Bus_Data<= BRAM_Dout; BRAM_WriteEnable<= Bus2IP_CS(0) and not Bus2IP_RNW; IP2Bus_WrAck<= BRAM_WriteEnable; process (Bus2IP_Clk) begin if Bus2IP_Clk 'event and Bus2IP_Clk ='1' then if Bus2IP_CS(0) = '1‘ and Bus2IP_RNW=‘1’ and IP2Bus_RdAck=‘0’ then IP2Bus_RdAck<= ‘1’; -- one clock delay for BRAM reading else IP2Bus_RdAck<= ‘0’; end if; end process;

AXI • AXI4 (Memory-Mapped), a robust memory-mapped interface designed to achieve maximum levels of on-chip performance. Allows variable bursts up to 256 data transfers per single address transfer. • AXI4-Lite, a lightweight, single-transaction memory-mapped interface. It is a smaller logic footprint, a subset of the AXI4 interface, used for accessing control registers and low-performance peripherals. • AXI4-Stream, used for high-speed streaming applications that do not require an address. Data burst size can be unlimited.

AXI - Architecture The AXI protocol is burst-based and defines the following independent transaction channels: • read address • read data • write address • write data • write response.

AXI – Point to Point connection

Prosty sposób transakcji - AXI Valid przed Ready Ready przed Valid

AXI – transaction handshaking Read Write may be before must be before

Address transaction The AXI protocol is burst-based. The master begins each burst by driving control information and the address of the first byte in the transaction to the slave. As the burst progresses, the slave must calculate the addresses of subsequent transfers in the burst. A burst must not cross a 4KB address boundary. Burst length The burst length is specified by: • ARLEN[7:0], for read transfers • AWLEN[7:0], for write transfers. Burst_Length = AxLEN[7:0] + 1

Number of bytes to transfer in each data transfer Burst size The maximum number of bytes to transfer in each data transfer, or beat, in a burst, is specified by: • ARSIZE[2:0], for read transfers • AWSIZE[2:0], for write transfers. AxSIZE[2:0] Bytes in transfer 0b000 1 0b001 2 0b010 4 0b011 8 0b100 16 0b101 32 0b110 64 0b111 128

Burst type FIXED In a fixed burst, the address is the same for every transfer in the burst. This burst type is used for repeated accesses to the same location such as when loading or emptying a FIFO. INCR Incrementing. In an incrementing burst, the address for each transfer in the burst is an increment of the address for the previous transfer. The increment value depends on the size of the transfer. For example, the address for each transfer in a burst with a size of four bytes is the previous address plus four. WRAP A wrapping burst is similar to an incrementing burst, except that the address wraps around to a lower address if an upper address limit is reached. AxBURST[1:0] Burst type 0b00 FIXED 0b01 INCR 0b10 WRAP 0b11 Reserved

Transaction ID The AXI protocol includes AXI ID transaction identifiers. By using AXI IDs, a master can issue transactions without waiting for earlier transactions to complete. This can improve system performance, because it enables parallel processing of transactions. There is no requirement for slaves or masters to use AXI transaction IDs. Masters and slaves can process one transaction at a time, meaning transactions are processed in the order they are issued. Transaction channel Transaction ID Write address channel AWID[3:0] Write data channel, AXI3 only WID[3:0] Write response channel BID[3:0] Read address channel ARID[3:0] Read data channel RID[3:0]

AXI Stream

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